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?2005 fairchild semiconductor corporation www.fairchildsemi.com rev.1.0.6 features ? internal avalanche rugged sense fet ? advanced burst-mode operation consumes under 1 w at 240vac & 0.5w load ? precision fixed operating frequency (66khz) ? internal start-up circuit ? pulse by pulse current limiting ? abnormal over current protection (aocp) ? over voltage protection (ovp) ? over load protection (olp) ? internal thermal shutdown function (tsd) ? auto-restart mode ? under voltage lock out (uvlo) with hysteresis ? low operating current (2.5ma) ? built-in soft start application ? smps for lcd monitor and stb ? adaptor description the fsdm07652r is an integrated pulse width modulator (pwm) and sense fet specifically designed for high performance offline switch mode power supplies (smps) with minimal external components. this device is an integrated high voltage power switching regulator which combine an avalanche rugged sense fet with a current mode pwm control block. the pwm controller includes integrated fixed frequency oscillator, under voltage lockout, leading edge blanking (leb), optimized gate driver, internal soft start, temperature compensated precise current sources for a loop compensation and self protection circuitry. compared with discrete mosfet and pwm controller solution, it can reduce total cost, component count, size and weight simulta- neously increasing efficiency, productivity, and system reliability. this device is a basic platform well suited for cost effective designs of flyback converters. table 1. notes: 1. typical continuous power in a non-ven- tilated enclosed adapter measured at 50 c ambient. 2. maximum practical continuous power in an open frame design at 50 c ambient. 3. 230 vac or 100/115 vac with doubler. typical circuit figure 1. typical flyback application output power table product 230vac 15% (3) 85-265vac adapt- er (1) open frame (2) adapt- er (1) open frame (2) fsdm0565r 60w 70w 50w 60w fsdm07652r 70w 80w 60w 70w drain source vstr vfb vcc pwm ac in dc out fsdm07652r green mode fairchild power switch (fps tm )
fsdm07652r 2 internal block diagram figure 2. functional block diagram of fsdm07652r 8v/12v 3 1 2 4 5 vref internal bias s q q r osc vcc vref i delay i fb v sd tsd vovp vcc vocp s q q r r 2.5r vcc good vcc drain n.c vfb gnd aocp gate driver 6 vstr i start vcc good 0.5/0.7v leb pwm soft start + - switching disable
fsdm07652r 3 pin definitions pin configuration figure 3. pin configuration (top view) pin number pin name pin function description 1drain this pin is the high voltage power sense fet drain. it is designed to drive the transformer directly. 2 gnd this pin is the control ground and the sense fet source. 3vcc this pin is the positive supply voltage input. during start up, the power is sup- plied by an internal high voltage current source that is connected to the vstr pin. when vcc reaches 12v, the internal high voltage current source is disabled and the power is supplied from the auxiliary transformer winding. 4vfb this pin is internally connected to the inverting input of the pwm comparator. the collector of an opto-coupler is typically tied to this pin. for stable operation, a capacitor should be placed between this pin and gnd. if the voltage of this pin reaches 6.0v, the over load protection is activated resulting in shutdown of the fps tm . 5n.c- 6vstr this pin is connected directly to the high voltage dc link. at startup, the internal high voltage current source supplies internal bias and charges the external ca- pacitor that is connected to the vcc pin. once vcc reaches 12v, the internal cur- rent source is disabled. 6.vstr 5.n.c. 4.vfb 3.vcc 2.gnd 1.drain to-220f-6l
fsdm07652r 4 absolute maximum ratings (ta=25 c, unless otherwise specified) notes: 1. repetitive rating: pulse width limited by maximum junction temperature 2. l=14mh, starting tj=25 c 3. l=13uh, starting tj=25 c thermal impedance notes: 1. free standing with no heat-sink under natural convection. 2. infinite cooling condition - refer to the semi g30-88. parameter symbol value unit drain-source voltage v dss 650 v vstr max voltage v str 650 v pulsed drain current (tc=25 c) (1) i dm 15 a dc continuous drain current(tc=25 c) i d 3.8 a continuous drain current(tc=100 c) 2.4 a single pulsed avalanche energy (2) e as 370 mj single pulsed avalanche current (3) i as -a supply voltage v cc 20 v input voltage range v fb -0.3 to v cc v total power dissipation(tc=25 c) p d (watt h/s) 45 w operating junction temperature t j internally limited c operating ambient temperature t a -25 to +85 c storage temperature range t stg -55 to +150 c esd capability, hbm model (all pins excepts for vstr and vfb) - 2.0 (gnd-vstr/vfb=1.5kv) kv esd capability, machine model (all pins excepts for vstr and vfb) - 300 (gnd-vstr/vfb=225v) v parameter symbol value unit junction-to-ambient thermal ja (1) 49.90 c/w junction-to-case thermal jc (2) 2.78 c/w
fsdm07652r 5 electrical characteristics (ta = 25 c unless otherwise specified) parameter symbol condition min. typ. max. unit sense fet section drain source breakdown voltage bv dss v gs = 0v, i d = 250 a 650 - - v zero gate voltage drain current i dss v ds = 650v, v gs = 0v - - 50 a v ds = 520v v gs = 0v, t c = 125 c - - 200 a static drain source on resistance (1) r ds(on) v gs = 10v, i d = 2.5a - 1.4 1.6 ? output capacitance c oss v gs = 0v, v ds = 25v, f = 1mhz - 100 - pf turn on delay time t d(on) v dd = 325v, i d = 5a (mosfet switching time is essentially independent of operating temperature) -22 - ns rise time t r -60 - turn off delay time t d(off) -115 - fall time t f -65 - control section initial frequency f osc v fb = 3v 60 66 72 khz voltage stability f stable 13v vcc 18v 0 1 3 % temperature stability (2) ? f osc -25 c ta 85 c0 510% maximum duty cycle d max -758085% minimum duty cycle d min ---0% start threshold voltage v start v fb =gnd 11 12 13 v stop threshold voltage v stop v fb =gnd 78 9v feedback source current i fb v fb =gnd 0.7 0.9 1.1 ma soft-start time t s v fb =3 - 10 15 ms leading edge blanking time t leb - - 250 - ns burst mode section burst mode voltages (2) v burh vcc=14v - 0.7 - v v burl vcc=14v - 0.5 - v protection section peak current limit (4) i over v fb =5v, v cc =14v 2.2 2.5 2.8 a over voltage protection v ovp -181920v abnormal over current protection current (3) i aocp - 5.54 6.15 6.77 a thermal shutdown temperature (2) t sd 130 145 160 c shutdown feedback voltage v sd v fb 5.5v 5.5 6.0 6.5 v
fsdm07652r 6 notes: 1. pulse test : pulse width 300 s, duty 2% 2. these parameters, although guaranteed at the design, are not tested in mass production. 3. these parameters, although guaranteed, are tested in eds(wafer test) process. 4. these parameters indicate the inductor current. 5. this parameter is the current flowing into the control ic. shutdown delay current i delay v fb =5v 2.8 3.5 4.2 a total device section operating supply current (5) i op v fb =gnd, v cc =14v -2.55ma i op(min) v fb =gnd, v cc =10v i op(max) v fb =gnd, v cc =18v
fsdm07652r 7 comparison between fs6m07652rtc and fsdm07652r function fs6m07652rtc fsdm07652r fsdm07652r advantages soft-start adjustable soft-start time using an external capacitor internal soft-start with typically 10ms (fixed) ? gradually increasing current limit during soft-start further reduces peak current and voltage component stresses ? eliminates external components used for soft-start in most applications ? reduces or eliminates output overshoot burst mode operation ? built into controller ? output voltage drops to around half ? built into controller ? output voltage fixed ? improve light load efficiency ? reduces no-load consumption
fsdm07652r 8 typical performance characteristics (these characteristic graphs are normalized at ta= 25 c) operating current vs. temp start threshold voltage vs. temp stop threshold voltage vs. temp operating freqency vs. temp maximum duty vs. temp feedback source current vs. temp 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -50 -25 0 25 50 75 100 125 junction temperature( ) operating current (normalized to 25 ) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -50 -25 0 25 50 75 100 125 junction temperature( ) start thershold voltage (normalized to 25 ) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -50 -25 0 25 50 75 100 125 junction temperature( ) stop threshold voltage (normalized to 25 ) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -50 -25 0 25 50 75 100 125 ju n c t ion te mpe ra tu re ( ) initial frequency (normalized to 25 ) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -50-250 255075100125 junction temperature( ) maximum duty cycle (normalized to 25 ) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -50 -25 0 25 50 75 100 125 junction temperature( ) fb source current (normalized to 25 )
fsdm07652r 9 typical performance characteristics (continued) (these characteristic graphs are normalized at ta= 25 c) shutdown feedback voltage vs. temp shutdown delay current vs. temp over voltage protection vs. temp burst mode enable voltage vs. temp burst mode disable voltage vs. temp current limit vs. temp 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -50 -25 0 25 50 75 100 125 junction temperature( ) shutdown fb voltage (normalized to 25 ) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -50 -25 0 25 50 75 100 125 junction temperature( ) shutdown delay current (normalized to 25 ) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -50 -25 0 25 50 75 100 125 junction temperature( ) over voltage protection (normalized to 25 ) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -50 -25 0 25 50 75 100 125 junction temperature( ) burst mode enable voltage (normalized to 25 ) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -50 -25 0 25 50 75 100 125 junction temperature( ) burst mode disable voltage (normalized to 25 ) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -50 -25 0 25 50 75 100 125 junc tion temperatu re( ) over current limit (normalized to 25 )
fsdm07652r 10 typical performance characteristics (continued) (these characteristic graphs are normalized at ta= 25 c) soft start time vs. temp 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -50 -25 0 25 50 75 100 125 junction temperature( ) soft start time (normalized to 25 )
fsdm07652r 11 functional description 1. 1. 1. 1. startup : in previous generations of fairchild power switches (fps tm ) the vcc pin had an external start-up resistor to the dc input voltage line. in this generation the startup resistor is replaced by an internal high voltage current source. at startup, an internal high voltage current source supplies the internal bias and charges the external capacitor (c vcc ) that is connected to the vcc pin as illustrated in figure 4. when vcc reaches 12v, the fps tm begins switching and the internal high voltage current source is disabled. then, the fps tm continues its normal switching operation and the power is supplied from the auxiliary transformer winding unless vcc goes below the stop voltage of 8v. figure 4. internal startup circuit 2. feedback control : fsdm07652r employs current mode control, as shown in figure 5. an opto-coupler (such as the h11a817a) and shunt regulator (such as the ka431) are typically used to implement the feedback network. comparing the feedback voltage with the voltage across the rsense resistor plus an offset voltage makes it possible to control the switching duty cycle. when the reference pin voltage of the ka431 exceeds the internal reference voltage of 2.5v, the h11a817a led current increases, thus pulling down the feedback voltage and reducing the duty cycle. this event typically happens when the input voltage is increased or the output load is decreased. 2.1 pulse-by-pulse current limit : because current mode control is employed, the peak current through the sense fet is limited by the inverting input of pwm comparator (vfb*) as shown in figure 5. assuming that the 0.9ma current source flows only through the internal resistor (2.5r +r= 2.8 k ? ), the cathode voltage of diode d2 is about 2.5v. since d1 is blocked when the feedback voltage (vfb) exceeds 2.5v, the maximum voltage of the cathode of d2 is clamped at this voltage, thus clamping vfb*. therefore, the peak value of the current through the sense fet is limited. 2.2 leading edge blanking (leb) : at the instant the internal sense fet is turned on, there usually exists a high current spike through the sense fet, caused by primary-side capacitance and secondary-side rectifier reverse recovery. excessive voltage across the rsense resistor would lead to incorrect feedback operation in the current mode pwm control. to counter this effect, the fps tm employs a leading edge blanking (leb) circuit. this circuit inhibits the pwm comparator for a short time (t leb ) after the sense fet is turned on. figure 5. pulse width modulation (pwm) circuit 3. protection circuit : the fsdm07652r has several self protective functions such as over load protection (olp), abnormal over current protection (aocp), over voltage protection (ovp) and thermal shutdown (tsd). because these protection circuits are fully integrated into the ic without external components, the reliability can be improved without increasing cost. once the fault condition occurs, switching is terminated and the sense fet remains off. this causes vcc to fall. when vcc reaches the uvlo stop voltage, 8v, the protection is reset and the internal high voltage current source charges the vcc capacitor via the vstr pin. when vcc reaches the uvlo start voltage,12v, the fps tm resumes its normal operation. in this manner, the auto-restart can alternately enable and disable the switching of the power sense fet until the fault condition is eliminated (see figure 6). 8v/12v 3 vref internal bias vcc 6 vstr i start vcc good v dc c vcc 4 osc vcc vref i delay i fb v sd r 2.5r gate driver olp d1 d2 + v fb * - vfb ka431 c b vo h11a817a r sense sensefet
fsdm07652r 12 figure 6. auto restart operation 3.1 over load protection (olp) : overload is defined as the load current exceeding a pre-set level due to an unexpected event. in this situation, the protection circuit should be activated in order to protect the smps. however, even when the smps is in the normal operation, the over load protection circuit can be activated during the load transition. in order to avoid this undesired operation, the over load protection circuit is designed to be activated after a specified time to determine whether it is a transient situation or an overload situation. because of the pulse-by-pulse current limit capability, the maximum peak current through the sense fet is limited, and therefore the maximum input power is restricted with a given input voltage. if the output consumes beyond this maximum power, the output voltage (vo) decreases below the set voltage. this reduces the current through the opto-coupler led, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (vfb). if vfb exceeds 2.5v, d1 is blocked and the 3.5ua current source starts to charge c b slowly up to vcc. in this condition, vfb continues increasing until it reaches 6v, when the switching operation is terminated as shown in figure 7. the delay time for shutdown is the time required to charge c b from 2.5v to 6.0v with 3.5ua. in general, a 10 ~ 50 ms delay time is typical for most applications. figure 7. over load protection 3.2 abnormal over current protection (aocp) : even though the fps tm has olp (over load protection) and current mode pwm feedback, these are not enough to protect the fps tm when a secondary side diode short or a transformer pin short occurs. the fps tm has an internal aocp (abnormal over current protection) circuit as shown in figure 8. when the gate turn-on signal is applied to the power sense fet, the aocp block is enabled and monitors the current through the sensing resistor. the voltage across the resistor is then compared with a preset aocp level. if the sensing resistor voltage is greater than the aocp level for longer than 300ns, the reset signal is applied to the latch, resulting in the shutdown of smps. figure 8. aocp block 3.3 over voltage protection (ovp) : if the secondary side feedback circuit were to malfunction or a solder defect caused an open in the feedback path, the current through the opto-coupler transistor becomes almost zero. then, vfb climbs up in a similar manner to the over load situation, forcing the preset maximum current to be supplied to the smps until the over load protection is activated. because more energy than required is provided to the output, the fault situation 8v 12v vcc vds t fault occurs fault removed normal operation normal operation power on v v v v fb fb fb fb t t t t 2.5v 2.5v 2.5v 2.5v 6.0v 6.0v 6.0v 6.0v over load protection over load protection over load protection over load protection t t t t 1 2 1 2 1 2 1 2 = cfb * (6.0-2.5) / i = cfb * (6.0-2.5) / i = cfb * (6.0-2.5) / i = cfb * (6.0-2.5) / i delay delay delay delay t t t t 1 1 1 1 t t t t 2 2 2 2 2 s q q r osc r 2.5r gnd gate driver leb pwm + - vaocp aocp r sense
fsdm07652r 13 output voltage may exceed the rated voltage before the over load protection is activated, resulting in the breakdown of the devices in the secondary side. in order to prevent this situation, an over voltage protection (ovp) circuit is employed. in general, vcc is proportional to the output voltage and the fps tm uses vcc instead of directly monitoring the output voltage. if v cc exceeds 19v, an ovp circuit is activated resulting in the termination of the switching operation. in order to avoid undesired activation of ovp during normal operation, vcc should be designed to be below 19v. 3.4 thermal shutdown (tsd) : the sense fet and the control ic are built in one package. this makes it easy for the control ic to detect the heat generation from the sense fet. when the temperature exceeds approximately 150 c, the thermal shutdown is activated. 4. soft start : the fps tm has an internal soft start circuit that increases pwm comparator inverting input voltage together with the sense fet current slowly after it starts up. the typical soft start time is 10msec, the pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. the voltage on the output capacitors is progressively increased with the intention of smoothly establishing the required output voltage. it also helps to prevent transformer saturation and reduce the stress on the secondary diode during startup. 5. burst operation : in order to minimize power dissipation in standby mode, the fps tm enters burst mode operation. as the load decreases, the feedback voltage decreases. as shown in figure 9, the device automatically enters burst mode when the feedback voltage drops below v burl (500mv). at this point switching stops and the output voltages start to drop at a rate dependent on standby current load. this causes the feedback voltage to rise. once it passes v burh (700mv) switching resumes. the feedback voltage then falls and the process repeats. burst mode operation alternately enables and disables switching of the power sense fet thereby reducing switching loss in standby mode. figure 9. waveforms of burst operation v fb vds 0.5v 0.7v ids vo vo set time switching disabled t1 t2 t3 switching disabled t4
fsdm07652r 14 typical application circuit features ? high efficiency (>81% at 85vac input) ? low zero load power consumption (<300mw at 240vac input) ? low standby mode power consumption (<800mw at 240vac input and 0.3w load) ? low component count ? enhanced system reliability through various protection functions ? internal soft-start (10ms) key design notes ? resistors r102 and r105 are employed to prevent start-up at low input voltage. after startup, there is no power loss in these resistors since the startup pin is internally disconnected after startup. ? the delay time for over load protection is designed to be about 50ms with c106 of 47nf. if a faster triggering of olp is required, c106 can be reduced to 10nf. ? zener diode zd102 is used for a safety test such as ul. when the drain pin and feedback pin are shorted, the zener diode fails and remains short, which causes the fuse (f1) blown and prevents explosion of the opto-coupler (ic301). this zener diode also increases the immunity against line surge. 1. schematic application output power input voltage output voltage (max current) lcd monitor 40w universal input (85-265vac) 5v (2.0a) 12v (2.5a) 3 4 c102 220nf 275vac lf101 23mh c101 220nf 275vac rt1 5d-9 f1 fuse 250v 2a c103 100uf 400v r102 30k ? ? ? ? r105 40k ? ? ? ? r103 56k ? ? ? ? 2w c104 2.2nf 1kv d101 uf 4007 c106 47nf 50v c105 22uf 50v d102 tvr10g r104 5 ? ? ? ? 1 2 3 4 5 t1 eer3016 bd101 2kbp06m 3n 257 1 2 r101 560k ? ? ? ? 1w ic1 fsdm 07652r vstr nc vfb vcc drain gnd 1 2 3 4 5 6 zd101 22v 8 10 d202 m brf10100 c201 1000uf 25v c202 1000uf 25v l201 12v, 2.5a 6 7 d201 m brf1045 c203 1000uf 10v c204 1000uf 10v l202 5v, 2a r201 1k ? ? ? ? r202 1.2k ? ? ? ? r204 5.6k ? ? ? ? r203 12k ? ? ? ? c205 47nf r205 5.6k ? ? ? ? c301 4.7nf ic301 h11a817a ic201 ka431 zd102 10v
fsdm07652r 15 2. transformer schematic diagram 3.winding specification 4.electrical characteristics 5. core & bobbin core : eer 3016 bobbin : eer3016 ae(mm2) : 96 no pin (s f) wire turns winding method na 4 50.2 1 8 center winding insulation: polyester tape t = 0.050mm, 2layers np/2 2 10.4 1 18 solenoid winding insulation: polyester tape t = 0.050mm, 2layers n12v 10 80.3 3 7 center winding insulation: polyester tape t = 0.050mm, 2layers n5v 7 60.3 3 3 center winding insulation: polyester tape t = 0.050mm, 2layers np/2 3 20.4 1 18 solenoid winding outer insulation: polyester tape t = 0.050mm, 2layers pin specification remarks inductance 1 - 3 520uh 10% 100khz, 1v leakage inductance 1 - 3 10uh max 2 nd all short eer3016 n p /2 n 12v n a 1 2 3 4 5 6 7 8 9 10 n p /2 n 5v
fsdm07652r 16 6.demo circuit part list part value note part value note fuse c301 4.7nf polyester film cap. f101 2a/250v ntc inductor rt101 5d-9 l201 5uh wire 1.2mm resistor l202 5uh wire 1.2mm r101 560k 1w r102 30k 1/4w r103 56k 2w r104 5 1/4w diode r105 40k 1/4w d101 uf4007 r201 1k 1/4w d102 tvr10g r202 1.2k 1/4w d201 mbrf1045 r203 12k 1/4w d202 mbrf10100 r204 5.6k 1/4w zd101 zener diode 22v r205 5.6k 1/4w zd102 zener diode 10v bridge diode bd101 2kbp06m 3n257 bridge diode capacitor c101 220nf/275vac box capacitor line filter c102 220nf/275vac box capacitor lf101 23mh wire 0.4mm c103 100uf/400v electrolytic capacitor ic c104 2.2nf/1kv ceramic capacitor ic101 fsdm07652r fps tm (7a,650v) c105 22uf/50v electrolytic capacitor ic201 ka431(tl431) voltage reference c106 47nf/50v ceramic capacitor ic301 h11a817a opto-coupler c201 1000uf/25v electrolytic capacitor c202 1000uf/25v electrolytic capacitor c203 1000uf/10v electrolytic capacitor c204 1000uf/10v electrolytic capacitor c205 47nf/50v ceramic capacitor
fsdm07652r 17 7. layout figure 10. layout considerations for fsdm07652r figure 11. layout considerations for fsdm07652r
fsdm07652r 18 package dimensions to-220f-6l(forming)
fsdm07652r 19 ordering information wdtu : forming type product number package marking code bvdss rds(on)max. FSDM07652RWDTU to-220f-6l(forming) dm07652r 650v 1.6 ?
fsdm07652r 1/12/05 0.0m 001 ? 2005 fairchild semiconductor corporation life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.

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